1. Field of the Invention
The present invention relates in general to reducing static power consumption of memory of an electronic device, and more specifically to reducing power consumption of active memory in an input/output (I/O) controller.
2. Description of the Related Art
An embedded memory constitutes a significant portion of the transistor budget in an input/output (I/O) controller or I/O controller functional unit a system on chip (SoC) device. The embedded memory is in one example configured as static random access memory (SRAM), which is often implemented with six transistor SRAM cells or the like. As feature sizes scale below 100 nanometers (nm), increasing leakage currents make static power consumption a significant concern, especially for integrated circuits (ICs) intended for battery-operated portable or handheld electronic devices. Existing techniques for reducing memory leakage currents concern reducing power consumption during sleep periods (when I/O activity cannot be underway). In conventional configurations, the entire memory is powered up and active in order to be available to perform memory operations with minimal latency thereby consuming a significant amount of power.